A Low-Power and High-Speed Frequency Multiplier for DLL-Based Clock Generator
نویسنده
چکیده
A low-power and high-speed frequency multiplier for a delay-locked loop-based clock generator is proposed to generate a multiplied clock with different range of frequencies. The modified edge combiner consumes low power and achieves a high-speed operation. The proposed frequency multiplier overcomes a deterministic jitter problem by reducing the delay difference between positiveand negative-edge generation paths. The proposed frequency multiplier is implemented in a 0.13-μm CMOS process technology achieved power consumption to a frequency ratio of 2.9 μW/MHz, and has the multiplication ratios of 16, and an output range of 100 MHz–3.3 GHz.
منابع مشابه
High Speed Delay-Locked Loop for Multiple Clock Phase Generation
In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Theref...
متن کاملHigh - Speed Frequency Multiplier Design for Dual Edge Detector Based Dll - Clock Generator
The aim of delay-locked loop-based clock generator to generate a multiplied clock with a high frequency and wide frequency range. The proposed edge combiner achieves a high-speed and highly reliable operation using a hierarchical structure and an overlap canceller. By applying the logic to the pulse generator and multiplication-ratio control logic design, the frequency of the delay is determine...
متن کاملLow Settling Time All Digital DLL For VHF Application
Settling time is one of the most important parameter in design of DLLs. In this paper we propose a new high speed with low settling time Delay Locked Loop (DLL) in which a digital signal processor (DSP) is used instead of using phase-frequency detector, charge pump and loop filter in conventional DLL. To have better settling time, PRP conjugate gradient algorithm is used to optimize delay of ea...
متن کاملA Digital Clock Multiplier for Globally Asynchronous Locally Synchronous Designs
For large high-speed globally synchronous ASICs, designing the clock distribution net becomes a troublesome task. Besides problems caused by clock skew, the clock net also is a major source of power consumption. Partitioning the design into locally clocked blocks reduces clock skew problems and if handled correctly it also reduces power consumption. However, to achieve these positive effects, t...
متن کاملModified 32-Bit Shift-Add Multiplier Design for Low Power Application
Multiplication is a basic operation in any signal processing application. Multiplication is the most important one among the four arithmetic operations like addition, subtraction, and division. Multipliers are usually hardware intensive, and the main parameters of concern are high speed, low cost, and less VLSI area. The propagation time and power consumption in the multiplier are always high. ...
متن کامل